李福乐

李福乐

个人简介

李福乐，男，浙江乐清人。1974年11月生。清华大学集成电路学院副研究员。于1996年7月和1999年4月分别获得西安电子科技大学工学学士和硕士学位，又于2003年4月获得清华大学工学博士学位，论文课题为流水线模数转换器的研究。从2003年4月至今，在清华大学微电子学研究所工作，研究内容包括数据转换器、传感器接口电路、射频收发机等模拟和数模混合集成电路设计，特别是高速高精度的流水线式模数转换器和电流舵式数模转换器。在相关领域发表论文近四十篇，申请专利20余项。

所发表的论文

[1] Peng Wang, Fule Li, Zhihua Wang. A Single-Channel 8-bit 1.6-GS/s Alternate-Comparator SAR ADC With Dither-Based Background Offset Calibration in 28-nm CMOS, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, pp.1-12( Early Access ), 2025.
[2] Chen Chen, Fangzhen Jiang, Peng Wang, Yongli Chen, Yan Xiao, Fule Li, Xiang Xie. A Reconfigurable Continuous-Time Delta-Sigma Modulator Structure Using Hybrid Loop Filter and Time-Interleaved Quantizer, ISCAS 2024, pp.1-5, Singapore, Singapore, 19-22 May. 2024.
[3] Peilin Yang, Fule Li, Zhihua Wang. A 14-Bit 4 GS/s Two-Way Interleaved Pipelined ADC With Aperture Error Tunning, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.71, No.6, pp.2961-2965, 2024.
[4] Yaning Wang, Yihang Cheng, Yongli Chen, Fule Li, Chun Zhang, Zhihua Wang. A Low Noise High Speed Dynamic Comparator Insensitive to PVT and Common-mode Input, NEWCAS 2023, pp.1-5, Edinburgh, UnitedKingdom, 26-28 Jun. 2023.
[5] Yaning Wang, Yihang Cheng, Yongli Chen, Fule Li, Chun Zhang, Zhihua Wang. A Low Noise High Speed Dynamic Comparator Insensitive to PVT and Common-mode Input, NEWCAS 2023, pp.1-5, Edinburgh, United Kingdom, 26-28 Jun. 2023.
[6] Junjie Jing, Yang Ding, Lingxiao Shen, Peng Wang, Fule Li. A Wide Input Common-mode Range Pipelined ADC Front-end with Common-mode Refreshing, NEWCAS 2023, pp.1-5, Edinburgh, United Kingdom, 26-28 Jun. 2023.
[7] Yihang Cheng, Yaning Wang, Fule Li, Chun Zhang, Zhihua Wang. High Linearity Front-End Circuit for RF Sampling ADCs with Nonlinear Junction Capacitor Cancellation, ISCAS 2023, pp.1-5, Monterey, CA, USA, 21-25 May. 2023.
[8] Yaoyu Li, Yanshu Guo, Wen Jia, Fule Li, Zhihua Wang, Hanjun Jiang. Current-Steering DAC Calibration Using Q-Learning, ISCAS 2023, pp.1-5, Monterey, CA, USA, 21-25 May. 2023.
[9] Yihang Cheng, Yaning Wang, Fule Li, Chun Zhang, Zhihua Wang. High Linearity Front-End Circuit for RF Sampling ADCs with Nonlinear Junction Capacitor Cancellation, ISCAS 2023, pp.1-5, Monterey, CA, USA, 21-25 May. 2023.
[10] Jingpeng Zhou, Peng Wang, Zhiqiang Luo, Fule Li. All-Digital Background Calibration of a Pipelined-SAR ADC Using the “Split ADC” Architecture, ISCAS 2023, pp.1-5, Monterey, CA, USA, 21-25 May. 2023.
[11] Yaning Wang, Zhenguo Li, Peng Wang, Yihang Cheng, Fule Li, Yi Hu, Jiali Hou, Meng Su, Mengjiao Li. A Floating-Ring Hybrid Amplifier Insensitive to PVT and Common-mode Variation without CMFB for High-Speed ADCs, ISCAS 2024, pp.1-5, Singapore, Singapore, 19-22 May. 2023.
[12] Junjie Jing, Lingxiao Shen, Fule Li, Chun Zhang, Zhihua Wang. BICMOS residue amplifier with base current compensation technique in High-speed Pipelined ADC, ICSICT 2022, pp.1-3, Nangjing, China, 25-28 Oct. 2022.
[13] Yihang Cheng, Lingxiao Shen, Fule Li, Chun Zhang, Zhihua Wang. An op-amp for 12bit 1.25GS/s pipelined ADC with negative impedance compensation in 65nm CMOS, ICSICT 2022, pp.1-3, Nangjing, China, 25-28 Oct. 2022.
[14] Zhiqiang Luo, Peng Wang, Fule Li, Chun Zhang, Zhihua Wang. A statistics-based background capacitor mismatch calibration algorithm for SAR ADC, ICTA 2022, pp.60-61, Xi'an, China, 28-30 Oct. 2022.
[15] Haoran Wang, Junjie Jing, Fule Li. A Self-Regulating Negative Charge Pump Using Multi-Phase Clock for Wideband ADCs, ISCAS 2022, pp.2525-2528, Austin, TX, USA, 27 May-01 Jun. 2022.
[16] Zhiqiang Luo, Hongyu Li, Junjie Jing, Yan Chen, Yutong Zhang, Fule Li. A Dual Mode SAR ADC with Oversampling and Dithering for Extended Accuracy, 2022 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), pp.1-4, Shenzhen, China, 11-13 Nov. 2022.
[17] Peilin Yang, Fule Li, Zhihua Wang. A 12-Bit 2-GS/s Pipelined ADC Front-End Stage with Aperture Error Tuning and Split MDAC, ISCAS 2021, pp.1-5, Daegu, Korea, 22-28 May 2021.
[18] Meng Ni, Xiao Wang, Fule Li, Woogeun Rhee, Zhihua Wang. A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.PP, No.99, pp.1-14, 2021.
[19] Meng Ni, Xiao Wang, Fule Li, Zhihua Wang. A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.29, No.7, pp.1416-1427, 2021.
[20] Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee, Zhihua Wang. A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique, MWSCAS 2020, pp. 341 - 344, Springfield, MA, USA, 9-12 Aug. 2020.
[21] Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee, Zhihua Wang. A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC, MWSCAS 2020, pp. 345 - 348, Springfield, MA, USA, 9-12 Aug. 2020.
[22] Xiao Wang, Fule Li, Zhihua Wang. A Simple Histogram-based Capacitor Mismatch Calibration in SAR ADCs, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.PP, No.99, pp. 1 - 1, 2020.
[23] Peilin Yang, Xiao Wang, Chengwei Wang, Fule Li, Hanjun Jiang, Zhihua Wang. A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.28, No.9, pp. 2004 - 2013, 2020.
[24] Shaoquan Gao, Hanjun Jiang, Fule Li, Zhihua Wang. A 530 nA quiescent current low-dropout regulator with embedded reference for wake-up receivers, Science China (Information Sciences), Vol.63, pp. 229404:1 - 229404:3, 2020.
[25] Zekai Wu, Fule Li, Meng Ni, Yang Ding, Zhihua Wang. A Background Timing Skew Calibration Technique in Time-Interleaved ADCs, EDSSC 2019, pp. 1 - 3, Xi'an, China, 12-14 June 2019.
[26] Lingxiao Shen, Fule Li, Zhihua Wang. A 10b 50 MS/s single-Channel asynchronous SAR ADC with two alternate comparators and comparator calibration, ICTA 2019, pp. 35 - 36, Chengdu, China, 13-15 Nov. 2019.
[27] Shaoquan Gao, Hanjun Jiang, Fule Li, Zhihua Wang. DCO gain calibration technique in fractional-N Δ-Σ PLL based two-point phase modulators, MWSCAS 2019, pp. 718 - 721, Dallas, TX, USA, 4-7 Aug. 2019.
[28] Xiao Wang, Fule Li, Wen Jia, Zhihua Wang. A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.66, No.3, pp. 322 - 326, 2019.
[29] Shaoquan Gao, Hanjun Jiang, Zhaoyang Weng, Yanshu Guo, Jingjing Dong, Fule Li, Zhihua Wang. A 7.9 μA multi-step phase-domain ADC for GFSK demodulators, Analog Integrated Circuits and Signal Processing, Vol.94, pp. 49 - 63, 2018.
[30] Zekai Wu, Chengwei Wang, Yang Ding, Fule Li, Zhihua Wang. An ADC Input Buffer with Optimized Linearity, ICSICT 2018, pp. 1 - 3, Qingdao, China, 31 Oct.-3 Nov. 2018.
[31] Xiao Wang, Chengwei Wang, Fule Li, Zhihua Wang. A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process, ISCAS 2018, pp. 1 - 5, Florence, Italy, 27-30 May 2018.
[32] Chengwei Wang, Xiao Wang, Yang Ding, Fule Li, Zhihua Wang. A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique, ISCAS 2018, pp. 1 - 5, Florence, Italy, 27-30 May 2018.
[33] Hongyu Li, Fule Li, Weitao Li, Hanjun Jiang, Zhihua Wang. Design of a 5GS/s 200 MHz BW 74.8 dB SNDR continuous-time sigma delta modulator in 28nm CMOS, ISNE 2018, pp. 1 - 4, Taipei, Taiwan, 7-9 May 2018.
[34] Zhaoyang Weng, Hanjun Jiang, Jingjing Dong, Yang Li, Jingyi Zheng, Yiyu Shen, Fule Li, Woogeun Rhee, Zhihua Wang. 400-MHz/2.4-GHz Combo WPAN Transceiver IC for Simultaneous Dual-Band Communication With One Single Antenna, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.65, No.2, pp. 745 - 757, 2018.
[35] Honghao Chu, Fule Li. A 14bit 320MS/s pipelined-SAR ADC based on multiplexing of dynamic amplifier, ASICON 2017, pp. 628 - 631, Guiyang, China, 25-28 Oct. 2017.
[36] Ruihan Pei, Jia Liu, Xian Tang, Fule Li, Zhihua Wang. A low-offset dynamic comparator with input offset-cancellation, ASICON 2017, pp. 132 - 135, Guiyang, China, 25-28 Oct. 2017.
[37] Weitao Li, Fule Li, Jia Liu, Hongyu Li, Zhihua Wang. A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator, A-SSCC 2017, pp. 225 - 228, Seoul, South Korea, 6-8 Nov. 2017.
[38] Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang. A 4–40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS, CICC 2017, pp. 1 - 4, Austin, TX, USA, 30 April-3 May 2017.
[39] Xuqiang Zheng, Fangxu Lv, Feng Zhao, Shigang Yue, Chun Zhang, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang. A 10 GHz 56 fsrms-integrated-jitter and ?247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS, CICC 2017, pp. 1 - 4, Austin, TX, USA, 30 April-3 May 2017.
[40] Jia Liu, Fule Li, Weitao Li, Hanjun Jiang, Zhihua Wang. A Flash ADC with low offset dynamic Comparators, EDSSC 2017, pp. 1 - 2, Hsinchu, Taiwan, 18-20 Oct. 2017.
[41] Jingjing Dong, Hanjun Jiang, Kai Yang, Zhaoyang Weng, Fule Li, Jianjun Wei, Yanqing Ning, Xinkai Chen, Zhihua Wang. A wireless body sound sensor with a dedicated compact chipset, Circuits Systems and Signal Processing, Vol.36, No.6, pp. 2341 - 2359, 2017.
[42] Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shuai Yuan, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang. A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS, IEEE Journal of Solid-State Circuits, Vol.52, No.11, pp. 2963 - 2978, 2017.
[43] Xiuju He, Xian Gu, Weitao Li, Hanjun Jiang, Fule Li, Zhihua Wang. An 11-bit 200MS/s Subrange SAR ADC with Low-Cost Integrated Reference Buffer, Journal of Semiconductors, Vol.38, No.10, pp. 88-93, 2017.
[44] Xiuju He, Chunying Xue, Ya Wang, Fule Li, Chun Zhang, Xueping Jiang. An 11bit 150MS/s Sub-range SAR ADC IP for Wireless Transceiver, Microelectronics & Computer, Vol.34, No.5, pp. 1 - 5, 2017.
[45] Meng Ni, Fule Li, Jia Zhou, Zhijun Wang, Chun Zhang, Xian Tang, Zhihua Wang. A 12Bit 800MS/s time-interleaving pipeline ADC in 65nm CMOS, EDSSC 2016, pp. 391 - 394, Hong Kong, 3-5 Aug. 2016.
[46] Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang. A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS, ESSCIRC 2016, pp. 305 - 308, Lausanne, Switzerland, 12-15 Sept. 2016.
[47] Ying Ju, Fule Li, Xian Gu, Chun Zhang, Zhihua Wang. Digital Calibration Technique for Subrange ADC Based on SAR Architecture, ISNE 2016, pp. 1 - 2, Hsinchu, Taiwan, 3-6 May 2016.
[48] Shushu Wei, Xian Gu, Fule Li, Zhihua Wang. An 11-bit 250MS/s subrange-SAR ADC in 40nm CMOS, ISNE 2016, pp. 1 - 2, Hsinchu, Taiwan, 3-6 May 2016.
[49] Ying Ju, Fule Li, XiuJu He, Chun Zhang, Zhihua Wang. Aperture Error Reduction Technique for Subrange SAR ADC, NEWCAS 2016, pp. 1 - 4, Vancouver, Canada, 26-29 Jun. 2016.
[50] Shushu Wei, XiuJu He, Fule Li, Zhihua Wang. An 11-bit 200MS/s Subrange SAR ADC with Charge-Compensation-Based Reference Buffer, NEWCAS 2016, pp. 1 - 4, Vancouver, Canada, 26-29 Jun. 2016.
[51] Zhaoming Wu, Chun Zhang, Fule Li, Zhihua Wang. High Speed Serial Interface Transceiver Controller Based on JESD204B, NEWCAS 2016, pp. 1 - 4, Vancouver, Canada, 26-29 Jun. 2016.
[52] Zhaoyang Weng, Hanjun Jiang, Jingjing Dong, Fule Li, Zhihua Wang. 400–450 MHz power amplifier with high-order harmonic suppression for multi-protocol transceiver, Electronics Letters, Vol.52, No.23, pp. 1927-1929, 2016.
[53] Zhaoyang Weng, Hanjun Jiang, Jingjing Dong, Fule Li, Zhihua Wang. 400–450 MHz power amplifier with high-order harmonic suppression for multi-protocol transceiver, Electronics Letters, Vol.52, No.23, pp. 1927 - 1929, 2016.
[54] Xuqiang Zheng, Zhijun Wang, Fule Li, Feng Zhao, Shigang Yue, Chun Zhang, Zhihua Wang. A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.63, No.9, pp. 1381 - 1392, 2016.
[55] Heng Liu, Hanjun Jiang, Jingpei Xia, Zhexiang Chi, Fule Li, Zhihua Wang. A Fully Integrated SoC for Smart Capsule Providing In-Body Continuous pH and Temperature Monitoring, Journal of Semiconductor Technology and Science, Vol.16, No.5, pp. 542 - 549, 2016.
[56] Xuqiang Zheng, Fule Li, Zhijun Wang, Weitao Li, Wen Jia, Zhihua Wang, Shigang Yue. An S/H circuit with parasitics optimized for IF-sampling, Journal of Semiconductors, Vol.37, No.6, pp. 065005-1 - 5, 2016.
[57] Xian Gu, Xiuju He, Fule Li. A Calibration Technique for SAR ADC Based on Code Density Test, ASICON 2015, pp. 1 - 4, Chengdu, China, 3-6 Nov. 2015.
[58] Meng Ni, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang. A High-Speed analog front-end circuit used in a 12bit 1GSps Pipeline ADC, ASICON 2015, pp. 1 - 4, Chengdu, China, 3-6 Nov. 2015.
[59] Weidong Cao, Xuqiang Zheng, Ziqiang Wang, Dongmei Li, Fule Li, Shigang Yue, Zhihua Wang. A 15Gb/s Wireline Repeater in 65nm CMOS Technology, EDSSC 2015, pp. 590 - 593, Singapore, 1-4 June 2015.
[60] Weidong Cao, Ziqiang Wang, Dongmei Li, Fule Li, Zhihua Wang. A 40Gb/s Adaptive Equalizer with Amplitude Approaching Technique in 65nm CMOS, EDSSC 2015, pp. 451 - 454, Singapore, 1-4 June 2015.
[61] Shihao You, Fule Li, Chun Zhang, Zhihua Wang. High speed serial interface transmitter controller based on JESD204B for 1GSPS ADCs, EDSSC 2015, pp. 87 - 90, Singapore, 1-4 Jun. 2015.
[62] Ya Wang, Fule Li, Chunying Xue, Zhihua Wang. Charge-compensation-based reference technique for switched-capacitor ADCs, ISCAS 2015, pp. 2257 - 2260, Lisbon, Portugal, 24-27 May 2015.
[63] Heng Liu, Hanjun Jiang, Kai Yang, Zhexiang Chi, Fule Li, Chun Zhang, Zhihua Wang. A Fully Integrated Wireless SoC for In-Body pH and Temperature Continuous Monitoring, ISOCC 2015, , Gyeongju, South Korea, 2-5 Nov. 2015.
[64] Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang. A 40Gb/s 39mW 3-tap Adaptive Closed-loop Feedback Equalizer in 65nm CMOS, MWSCAS 2015, pp. 1 - 4, Fort Collins, Colorado USA, 2-5 Aug. 2015.
[65] Jifang Wu, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang. A 14-bit 200MS/s low-power pipelined flash-SAR ADC, MWSCAS 2015, pp. 1 - 4, Fort Collins, CO, 2-5 Aug. 2015.
[66] Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Ke Huang, Shuai Yuan, Fule Li, Zhihua Wang. A 40Gb/s 27mW 3-tap Closed-loop Decision Feedback Equalizer in 65nm CMOS, NEWCAS 2015, pp. 1 - 4, Grenoble, France, 7-10 Jun. 2015.
[67] Weitao Li, Fule Li, Ya Wang, Shengjing Li, Chun Zhang, Zhihua Wang. A power-efficient 14-bit 250MS/s pipelined ADC, NEWCAS 2015, pp. 1 - 4, Grenoble, France, 7-10 Jun. 2015.
[68] Shengjing Li, Weitao Li, Fule Li, Zhihua Wang, Chun Zhang. A digital blind background calibration algorithm for pipelined ADC, NEWCAS 2015, pp. 1 - 4, Grenoble, France, 7-10 Jun. 2015.
[69] Weitao Li, Fule Li, Changyi Yang, Shengjing Li, Zhihua Wang. An 85mW 14-bit 150MS/s pipelined ADC with a merged first and second MDAC, China Communications, Vol.12, No.5, pp. 14 - 21, 2015.
[70] Weitao Li, Fule Li, Changyi Yang, Shengjing Li, Zhihua Wang. A 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC, China Communications, Vol.12, No.5, pp. 14 - 21, 2015.
[71] Qi Peng, Chun Zhang, Xijin Zhao, Xuguang Sun, Fule Li, Hong Chen, Zhihua Wang. A Low-Cost UHF RFID System With OCA Tag for Short-Range Communication, IEEE Transactions on Industrial Electronics, Vol.62, No.7, pp. 4455 - 4465, 2015.
[72] Weitao Li, Fule Li, Changyi Yang, Minzeng Li, Zhihua Wang. A power-efficient reference buffer with wide swing for switched-capacitor ADC, Microelectronics Journal, Vol.46, No.5, pp. 410 - 414, 2015.
[73] Ya Wang, Chunying Xue, Fule Li, Chun Zhang, Zhihua Wang. A low power 11-bit 100 MS/s SAR ADC IP, Journal of Semiconductors, Vol.36, No.2, pp. 025003-1-5, 2015.
[74] Jia Zhou, Lili Xu, Fule Li, Zhihua Wang. A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy, Journal of Semiconductors, Vol.36, No.8, 2015.
[75] Ya Wang, Chunying Xue, Fule Li, Chun Zhang, Zhihua Wang. A low power 11-bit 100MS/s SAR ADC IP, Journal of Semiconductors, Vol.36, No.2, pp. 025003-5, 2015.
[76] Lili Xu, Chenchen Zhao, Fule Li, Chun Zhang, Zhihua Wang. A improved frontend for high-speed SHA-less pipelined ADC, EDSSC 2014, pp. 1 - 2, Chengdu, China, 18-20 Jun. 2014.
[77] Jifang Wu, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang. A 14b 200MHz power-efficient pipelined flash-SAR ADC, ICSICT 2014, pp. 1 - 3, Guilin, China, 28-31 Oct. 2014.
[78] Jifang Wu, Fule Li, Chun Zhang. An asynchronous SAR ADC with gate-controlled ring oscillator for multi-phase clock generator, ICSICT 2014, pp. 1 - 3, Guilin, China, 28-31 Oct. 2014.
[79] Chunying Xue, Ya Wang, Fule Li, Chun Zhang, Zhihua Wang. An 11-bit 200MS/s SAR ADC IP for Wireless Communication SOC, ICSICT 2014, pp. 1 - 3, Guilin, China, 28-31 Oct. 2014.
[80] Jingjing Dong, Hanjun Jiang, Lingwei Zhang, Jianjun Wei, Fule Li, Chun Zhang, ZhiHua Wang. A low-power DC offset calibration method independent of IF gain for zero-IF receiver, Science China-Information Sciences, Vol.57, No.10, pp 1 - 10, 2014.
[81] Minzeng Li, Fule Li, Chun Zhang, Zhihua Wang. Pixel-level A/D conversion using voltage reset technique, Journal of Semiconductors, Vol.35, No.11, pp. 115009-1-5, 2014.
[82] Ning Xu, Fule Li, Chun Zhang, Zhihua Wang. An IP-oriented 11-bit 160 MS/s 2-channel current-steering DAC, Journal of Semiconductors, Vol.35, No.12, pp. 125011-1-5, 2014.
[83] Yang Yang, Fule Li, Chun Zhang. Design of a 16-bit 1GSPS Current-Steering D-to-A Converter, Microelectronics, Vol.44, No.3, 2014.
[84] Minzeng Li, Fule Li, Chun Zhang. Pixel-level A/D Conversion Using Charge Reset Technique, Semiconductor Technology, Vol.39, No.9, pp. 656 - 660+665, 2014.
[85] Changyi Yang, Fule Li, Weitao Li, Xuan Wang, Zhihua Wang. An 85mW 14-bit 150MS/s Pipelined ADC with 71.3dB Peak SNDR in 130nm CMOS, A-SSCC 2013, pp. 85 - 88, Singapore, 11-13 Nov. 2013.
[86] Changyi Yang, Weitao Li, Fule Li, Zhihua Wang. A Merged First and Second Stage for Low Power Pipelined ADC, ISCAS 2013, pp. 153 – 156, Beijing, China, 19-23 May 2013.
[87] Lingwei Zhang, Hanjun Jiang, Fule Li, Jingjing Dong, Zhihua Wang. A LUT-free DC Offset Calibration Method for removing the PGA-gain-correlated Offset Residue, ISCAS 2013, pp. 1704 - 1707, Beijing, China, 19-23 May 2013.
[88] Weitao Li, Cao Sun, Fule Li, Zhihua Wang. A 14-bit Pipelined ADC with Digital Background Nonlinearity Calibration, ISCAS 2013, pp. 2448 - 2451, Beijing, China, 19-23 May 2013.
[89] Chenchen Zhao, Lili Xu, Fule Li, Zhihua Wang. An efficient calibration technique for pipeline ADC, MWSCAS 2013, pp. 669 – 672, Columbus, Ohio, USA, 4-7 Aug. 2013.
[90] Zhihua Wang, Hanjun Jiang, Kai Yang, Lingwei Zhang, Jianjun Wei, Fule Li, Baoyong Chi, Chun Zhang, Shouhao Wu, Qingliang Lin, Wen Jia. Lifetime Tracing of Cardiopulmonary Sounds with Ultra-Low-Power Sound Sensor Stick Connected to Wireless Mobile Network, NEWCAS 2013, pp. 1 - 4, Paris, 16-19 June 2013.
[91] Lingwei Zhang, Hanjun Jiang, Fule Li, Jingjing Dong, Jianwei Cui, Zhihua Wang. DC offset calibration method for zero-IF receiver removing the PGA-gain-correlated offset residue, AEU-International Journal of Electronics and Communications, Vol.67, No.7, pp. 578 - 584, 2013.
[92] Lingwei Zhang, Hanjun Jiang, Jianjun Wei, Jingjing Dong, Fule Li, Weitao Li, Jia Gao, Jianwei Cui, Baoyong Chi, Chun Zhang, Zhihua Wang. A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO, IEEE Journal of Solid-State Circuits, Vol.48, No.11, pp. 2705 - 2716, 2013.
[93] Meng Yu, Lipeng Wu, Fule Li, Zhihua Wang. An 8 bit 12 MS/s asynchronous successive approximation register ADC with an on-chip reference, Journal of Semiconductors, Vol.34, No.2, pp. 025010-1-5, 2013.
[94] Jianjun Wei, Hanjun Jiang, Lingwei Zhang, Jinjin Dong, Fule Li, Zhihua Wang, Chun Zhang. A wide range sigma-delta fractional-N frequency synthesizer with adaptive frequency calibration, Journal of Semiconductors, Vol.34, No.6, pp. 065002-1-5, 2013.
[95] Lingwei Zhang, Hanjun Jiang, Jianjun Wei, Jingjing Dong, Weitao Li, Jia Gao, Jianwei Cui, Fule Li, Baoyong Chi, Chun Zhang, Zhihua Wang. A low-power reconfigurable multi-band sliding-IF transceiver for WBAN Hubs in 0.18μm CMOS, A-SSCC 2012, pp. 77 - 80, Kobe, Japan, 12-14 Nov. 2012.
[96] Ruihao Si, Fule Li, Chun Zhang. A 100MHz S/s, 7 bit VCO-based ADC which is used in Time Interleaved ADC Architectures, CECNet 2012, pp. 4 - 7, YiChang, Hubei, China, 21-23 April 2012.
[97] Wu Chao, Fule Li. A New Calibration Technique for Pipelined A/D Converters, ICETCE 2012, , Three Gorges, Hubei, China, 18-20 May 2012.
[98] Lipeng Wu, Meng Yu, Fule Li. An on-chip smart temperature sensor based on band gap and SAR ADC, ICSICT 2012, pp. 1 - 3, Xi'an, China, 29 Oct.-1 Nov. 2012.
[99] Cao Sun, Fule Li, Weitao Li, Hanjun Jiang. A configurable active-RC filter for half-duplex transceiver, ICSICT 2012, pp. 1 - 3, Xi'an, China, 29 Oct.-1 Nov. 2012.
[100] Xuan Wang, Changyi Yang, Xiaoxiao Zhao, Chao Wu, Fule Li, Zhihua Wang, Bin Wu. A 12-bit, 270MS/s Pipelined ADC with SHA-Eliminating Front End, ISCAS 2012, pp. 798 – 801, Seoul, Korea, 20-23 May 2012.
[101] Shaopeng Wang, Yannan Ren, Fule Li, Zhihua Wang. A 400MS/s 12-bit current-steering D/A Converter, Chinese Journal of Semiconductors, Vol.33, No.8, pp. 085006-1-5, 2012.
[102] Jianjian Shao, Weitao Li, Cao Sun, Fule Li, Chun Zhang, Zhihua Wang. A digital background calibration algorithm of a pipeline ADC based on output code calculation, Chinese Journal of Semiconductors, Vol.33, No.11, pp. 115010-1-5, 2012.
[103] Binjie Zhu, Ziqi Song, Dongxu Yang, Yafei Ye, Fule Li. A 8-bit 200MSmaple/s CMOS DAC, ASID 2011, pp. 198 - 200, Xiamen, China, 24-26 June 2011.
[104] Yafei Ye, Liyuan Liu, Fule Li, Dongmei Li, Zhihua Wang. An 8-bit 1MHz Successive Approximation Register (SAR) A/D with 7.98 ENOB, ASID 2011, pp. 139 - 142, Xiamen, China, 24-26 June 2011.
[105] Ting Li, Fule Li, Chun Zhang, Zhihua Wang. A 14bit 10MSps Low Power Pipelined ADC With 0.99pJ/step FOM, ASID 2011, pp. 150 - 153, Xiamen, China, 24-26 June 2011.
[106] Xiaoxiao Zhao, Fule Li, Bin Wu. A SHA-less 12-bit 200-MS/s pipeline ADC, ASID 2011, pp. 161 - 164, Xiamen, China, 24-26 June 2011.
[107] Ying Cheng, Fule Li, Xuqiang Zheng, Chun Zhang. Self-Calibrating On-Chip Termination Resistor for High-Speed SerDes, CECNet 2011, pp. 5207 - 5210, Xianning, Hubei, 16-18 April 2011.
[108] Shun Zhang, Weitao Li, Fule Li. A 400-440MHz Power Amplifier for Single-chip Wireless Transceiver, ITC-CSCC 2011, , Gyeongju, Korea, 19-22 June 2011.
[109] Binjie Zhu, Hanjun Jiang, Liyuan Liu, Jigang Shao, Liwei Deng, Fule Li, Chun Zhang, Zhihua Wang. A Wireless SoC for Alimentary Canal pH Value Continuously Monitoring, MWSCAS 2011, pp. 1 - 4, Seoul, Korea, 7-10 Aug. 2011.
[110] Kaimin Zhou, Ziqiang Wang, Fule Li, Chun Zhang, Zhihua Wang. A low-power high-linearity symmetrical readout circuit for capacitive sensors, MWSCAS 2011, pp. 1 - 4, Seoul, Korea, 7-10 Aug. 2011.
[111] Xiaoyu Zhang, Hanjun Jiang, Songyuan Cheng, Lingwei Zhang, Fule Li, Chun Zhang, Zhihua Wang. A High-Efficiency Work-on-Demand SoC with a 0.9V/165 mu W MCU and Dual-Band RF for WBSN, Chinese Journal of Electronics, Vol.20, No.1, pp. 21 - 26, 2011.
[112] Hanjun Jiang, Fule Li, Xinkai Chen, Yanqing Ning, Xu Zhang, Bin Zhang, Teng Ma, Zhihua Wang. A SoC with 3.9mW 3Mbps UHF Transmitter and 240μW MCU for Capsule Endoscope with Bidirectional Communication, A-SSCC 2010, pp. 1 - 4, Beijing, 8-10 Nov. 2010.
[113] Xiaoyu Zhang, Hanjun Jiang, Fule Li, Songyuan Cheng, Chun Zhang, Zhihua Wang. An Energy-Efficient SoC for Closed-Loop Medical Monitoring and Intervention, CICC 2010, pp. 1 - 4, San Jose, CA, 19-22 Sept 2010.
[114] Xiaobo Cai, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang. A 12bit 100MSps Pipelined ADC without Calibration, CISP 2010, pp. 3547 - 3552, Yantai, 16-18 Oct. 2010.
[115] Shaopeng Wang, Yannan Ren, Changyi Yang, Fule Li, Zhihua Wang. A 200MS/s 10-bit Current-steering D/A Converter with On-chip Testbench, ICSICT 2010, pp. 296 - 298, Shanghai, 1-4 Nov. 2010.
[116] Changyi Yang, Xiaoxiao Zhao, Fule Li, Zhihua Wang. OTACAD：An Opamp Synthesis Tool Based on Simulation and Lookup Table, ICSICT 2010, pp. 803 - 805, Shanghai, 1-4 Nov. 2010.
[117] Linlin Chen, Ziqiang Wang, Chen Jia, Fule Li, Wenhan Hao, Bin Xiao, Chun Zhang, Zhihua Wang. A RF Remote-Control Transceiver with Zero-Standby Power Based on RFID Technology, PrimeAsia 2010, pp. 243 - 246, Shanghai, China, 22-24 Sept. 2010.
[118] Xiaoyu Zhang, Hanjun Jiang, Songyuan Cheng, Lingwei Zhang, Fule Li, Chun Zhang, Zhihua Wang. A High-Efficiency Work-on-Demand SoC with a 0.9V/165μW MCU and Dual-Band RF for WBSN, Chinese Journal of Electronics, pp. 1 - 4, 2010.
[119] Weitao Li, Fule Li, Dandan Guo, Chun Zhang, Zhihua Wang. An Undersampling 14-bit Cyclic ADC with over 100-dB SFDR, Chinese Journal of Semiconductors, Vol.31, No.2, pp. 025008-1-6, 2010.
[120] Yi Chen, Fule Li, Hong Chen, Chun Zhang, Zhihua Wang. A low power cyclic ADC design for a wireless monitoring system for orthopedic implants, Chinese Journal of Semiconductors, Vol.30, No.8, pp. 147 - 152, 2010.
[121] Xiaobo Cai, Fule Li. Design of High-Speed High-Resolution Pipelined ADC, Electronic Engineering & Product World, pp. 25 - 31, 2010.
[122] Linlin Chen, Ziqiang Wang, Chen Jia, Fule Li, Wenhan Hao, Guannan Xu, Chun Zhang, Zhihua Wang. Zero static power remote control system and the realization of transmitter, , pp. 171 - 175, 2010.
[123] Weitao Li, Fule Li, Dandan Guo, Chun Zhang, Zhihua Wang. An Undersampling 14-bit Cyclic ADC, ASICON 2009, pp. 211 - 214, Changsha, Hunan, 20-23 Oct. 2009.
[124] Yannan Ren, Fule Li, Chun Zhang, Zhihua Wang. A 400MS/s 10-bit current-steering D/A Converter, ICCCAS 2009, pp. 533 - 536, Milpitas, CA, 23-25 July 2009.
[125] Weitao Li, Fule Li, Chun Zhang, Zhihua Wang. A Digital Background Calibration Algorithm Based on Code Occurrence Count for Pipelined ADCs, ICCCAS 2009, pp. 550 - 553, Milpitas, CA, 23-25 July 2009.
[126] Qiuling Zhu, Chun Zhang, Zhongqi Liu, Jingchao Wang, Fule Li, Zhihua Wang. A Robust Radio Frequency Identification System Enhanced with Spread Spectrum Technique, ISCAS 2009, pp. 37 - 40, Taiwan, 24 May 2009.
[127] Qiuling Zhu, Chun Zhang, Xiaohui Wang, Ziqiang Wang, Fule Li, Zhihua Wang. VLSI Design of Spread Spectrum Encoding Low Power RFID Tag Baseband Processor, VLSI-DAT 2009, pp. 191 – 194, Taiwan, 28-30 Apr. 2009.
[128] Jingyi Guo, Dongmei Li, Liyuan Liu, Fule Li. The hardware realization of a digital background calibration technique for pipelined A/D converters, Chinese High Technology Letters, Vol.19, No.3, pp. 290 - 294, 2009.
[129] Dandan Guo, Fule Li, Chun Zhang, Zhihua Wang. A 13-bit, 8 MSample/s Pipeline A/D Converter, Chinese Journal of Semiconductors, Vol.30, No.2, pp. 0250061 - 5, 2009.
[130] Yi Chen, Fule Li, Hong Chen, Chun Zhang, Zhihua Wang. A Low Power Cyclic ADC Design for the Wireless Monitoring System of the Orthopedic Implants, Chinese Journal of Semiconductors, Vol.30, No.8, pp. 147 - 152, 2009.
[131] Jingchao Wang, Chun Zhang, Baoyong Chi, Ziqiang Wang, Fule Li, Zhihua Wang. A Low Cost Integrated Transceiver for Mobile UHF Passive RFID Reader Applications, Chinese Journal of Semiconductors, Vol.30, No.9, pp. 095007 - 1 - 5, 2009.
[132] Guoru Li, Guolin Li, Dongmei Li, Fule Li, Baoyong Chi, Chun Zhang. A multi-standard RF filter in UMC0.18um CMOS technology, Microelectronics, Vol.5, pp. 54 - 58, 2009.
[133] Rui Guo, Fule Li, Chun Zhang. Design of A 13-bit 50MS/s CMOS Pipelined ADC, Semiconductor Technology, Vol.34, No.10, pp. 1022 - 1026, 2009.
[134] Dandan Guo, Fule Li, Jingbo Duan, Chun Zhang, Zhihua Wang. A 13-bit CMOS pipeline analog-to-digital converter with improved sampling circuits, ICCCAS 2008, pp. 1048 - 1052, Xiamen, China, 25-27 May 2008.
[135] Shuaiqi Wang, Fule Li, Yasuaki Inoue. A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, pp. 2465 - 2474, 2008.
[136] Fule Li, Jingbo Duan, Zhihua Wang. A Capacitor Paring Technique for Capacitor Mismatch Reduction, Acta Electronica Sinica, Vol.36, No.2, pp. 338 - 341, 2008.
[137] Fule Li, Jingbo Duan, Zhihua Wang. A High Linearity,13bit Pipelined CMOS ADC, Chinese Journal of Semiconductors, Vol.29, No.3, pp. 497 - 501, 2008.
[138] Chao Sun, Dongmei Li, Liyuan Liu, Fule Li. A 14-Bit 20 MS/s CMOS Pipelined A/D Converter, Microelectronics, Vol.38, No.3, pp. 320 - 325, 2008.
[139] Jingbo Duan, Fule Li, Liyuan Liu, Dongmei Li, Yongmin Li, Zhihua Wang. A pipelined A/D conversion technique with low INL and DNL, ISCAS 2007, pp. 3391 - 3394, New Orleans, LA, 27-30 May 2007.
[140] Fule Li, Zhihua Wang, Dongmei Li. An incomplete settling technique for pipelined analog-to-digital converters, ISCAS 2007, pp. 3950 - 3953, New Orleans, LA, 27-30 May 2007.
[141] Hongmei Wang, Fule Li, Guolin Li, Zhihua Wang. Resolution analysis of the first stage in the high precision pipelined ADCs, Chinese Journal of Electronics, Vol.15, No.1, pp. 47 - 50, 2006.
[142] Fule Li, Hongmei Wang, Dongmei Li, Zhihua Wang. Low power 13bit 10^7 sample/s A/D converter, Journal of Tsinghua University (Science and Technology), Vol.46, No.1, pp. 115 - 118, 2006.
[143] Hongmei Wang, Fule Li, Dongmei Li, Zhihua Wang. A Speed Analysis Methodology for Pipelined A/D Converters, Journal of University of Electronic Science and Technology of China, Vol.35, No.6, pp. 913 - 916, 2006.
[144] Xin Zhang, Fule Li, Zhihua Wang. A Nonlinear Background Calibration Technique for Pipelined A/D, Microelectronics, pp. 2176 - 2180, 2006.
[145] Fule Li, Dongmei Li, Chun Zhang, Zhihua Wang. Capacitor Error Averaging Technique for Pipelined ADCs, Journal of Tsinghua University (Science and Technology), Vol.43, No.1, pp. 63 - 66, 2003.
[146] Fule Li, Dongmei Li, Chun Zhang, Zhihua Wang. A Capacitor Mismatch Calibration Technique for Pipelined A/D Conversion, Acta Electronica Sinica, Vol.30, No.11, pp. 1 - 3, 2002.
[147] Fule Li, Dongmei Li, Chun Zhang, Zhihua Wang. An Improved Capacitor Averaging Technique for Pipelined ADCs, Acta Electronica Sinica, Vol.30, No.9, pp. 1285 - 1287, 2002.
[148] Fule Li, Dongmei Li, Zhihua Wang. Novel method for improving the speed of pipelined A/D converters, Journal of Tsinghua University (Science and Technology), Vol.42, No.1, pp. 7 - 10, 2002.

所持有的专利

[1] 李福乐，池保勇，何金媚，周科吉，袁胜丽，张跃. 第一级跨导电流复用的两级放大器电路: 中国, 202410701039.X[P].
[2] 陈永利，蒋方震，陈晨，李福乐，肖衍. 调制器电路、数据转换器、通信组件、芯片及电子设备: 中国, 202410617642.X[P].
[3] 李福乐，池保勇，张蕊，周科吉，袁胜丽，张跃. 基于电容浮动顶板的模数转换器前端电路结构: 中国, 202410467065.0[P].
[4] 李福乐，池保勇，沈凌霄，周科吉，袁胜丽，张跃. 一种部分积求和阵列设计方法及相关组件: 中国, 202410312973-2[P].
[5] 李福乐，池保勇，沈凌霄，周科吉，袁胜丽，张跃. 基于输出采样反馈的低噪声参考驱动电路: 中国, 202410243691.1[P].
[6] 李福乐，王毅，池保勇，周科吉，袁胜丽，张跃. 基于Dummy比较器的模数转换装置、方法、设备及介质: 中国, 202410234079.8[P].
[7] 李福乐，丁洋，池保勇，周科吉，袁胜丽，张跃. 信号产生电路、全并行模数转换器及相关设备: 中国, 202410038703.7[P].
[8] 杨沛霖，李福乐，王志华. 第一级堆叠的低功耗电压放大电路: 中国, 202311258125.X[P].
[9] 李福乐，王雅宁. 应用于动态比较器的前置放大器及相关设备: 中国, 202310827835.3[P].
[10] 杨沛霖，李福乐，池保勇，周科吉，袁胜丽，张跃. 可进行信号跟踪的无静态功耗电压比较电路: 中国, 202310380280.2[P].
[11] 李福乐，王艺谋. 基于同步时钟异步转换的电荷复位式像素级数字化电路: 中国, 202310326982.2[P].
[12] 李福乐，周喆. 一种基于过采样的多路异步信号单信道数据传输电路: 中国, 202111563325.7[P].
[13] 李福乐，周喆. 一种基于分频的低功耗、低电源抖动TSV通孔数据传输电路: 中国, 202111333647.2[P].
[14] 杨沛霖，李福乐，王志华. 基于双输入跨导运放的电容分裂结构开关电容放大电路: 中国, 202110505925.1[P]. 2022-11-11.
[15] 李福乐，倪萌，丁洋. 一种TI-ADC通道间时序偏差校准方法: 中国, 202010707597.9[P]. 2022-11-11.
[16] 李福乐，丁洋，王晓. 一种宽带低功耗比较器电路: 中国, 202010403259.6[P]. 2022-4-15.
[17] 李福乐，丁洋. 具有抖动功能的阈值电压产生电路、FlashADC及流水线ADC: 中国, 202010130663.0[P]. 2021-08-24.
[18] 李福乐，周喆. 曲率补偿低温漂带隙基准电压源电路: 中国, 202010130680.4[P]. 2021-05-14.
[19] 李福乐，刘佳. 一种高速的CMOS传输门开关电路: 中国, 201711453695.9[P]. 2021-05-07.
[20] 李福乐，王成伟，贾雯，王志华. 提高流水线模数转换器输出精度的方法及模数转换器: 中国, 201710743591.5[P]. 2020-12-08.
[21] 王志华，姜汉钧，杨闻笛，张春，李福乐. 动态调整电极配置的植入式动态心电监测仪: 中国, 201710518009.5[P]. 2020-02-21.
[22] 李福乐，王晓，贾雯，王志华. 流水线模数转换器及其运放自适应配置电路及方法: 中国, 201710326116.8[P]. 2022-04-01.
[23] 李福乐，刘佳，贾雯，王志华. 参考电压驱动电路: 中国, 201710326104.5[P]. 2020-03-24.
[24] 董晶晶，姜汉钧，高绍全，翁兆洋，李福乐，王志华. 一种相位域模数转换器: 中国, 201710154193.X[P]. 2020-05-19.
[25] 吕方旭，王自强，张春，王志华，李福乐. 一种高速低功耗PAM4发射机: 中国, 201611104172.9[P]. 2018-11-20.
[26] 王自强，周宇星，张春，王志华，李福乐. 一种采用数字电路补偿电容的低压差线性稳压器: 中国, 201611105561.3[P]. 2017-12-19.
[27] 王自强，周宇星，张春，王志华，李福乐. 一种采用模拟电路补偿电容的低压差线性稳压器: 中国, 201611104762.1[P]. 2017-12-19.
[28] 吕方旭，王自强，张春，王志华，李福乐. 一种高速合路器: 中国, 201611104765.5[P]. 2019-07-12.
[29] 贺娅君，王自强，李宇根，刘晗，张春，王志华，李福乐. 一种支持多协议的锁相环: 中国, 201611104156.X[P]. 2018-10-19.
[30] 王自强，周乃文，吕方旭，张春，王志华，李福乐. 一种带有时序校准的发射机: 中国, 201611104171.4[P]. 2020-10-27.
[31] 李福乐, 巨颖. 输入采样与转换前端电路: 中国, 201610140328.2[P]. 2020-06-02.
[32] 曹卫东, 王自强, 郑旭强, 黄柯, 李福乐. 一种高速电路的带上拉PMOS管的动态锁存器: 中国, 201510497993.2[P]. 2017-12-29.
[33] 唐仙, 李福乐, 张春, 王志华. 电阻型温度传感芯片的校准电路和校准方法: 中国, 201510213973.8[P]. 2017-11-28.
[34] 李福乐, 张春, 王志华. 带有高频补偿的模拟电压缓冲器电路: 中国, 201410359994.6[P]. 2017-09-22.
[35] 李福乐, 吴积方. 用于异步逐步逼近模数转换器的多相时钟产生电路: 中国, 201310714734.1[P]. 2017-01-11.
[36] 郑旭强, 黄柯, 李福乐, 王自强, 张春, 王志华. 源同步高速串行接口的时钟通路前端放大电路: 中国, 201310629540.1[P]. 2016-08-17.
[37] 李福乐, 许丽丽, 张春, 王志华. 模数转换器前端电路: 中国, 201310217847.0[P]. 2016-06-01.
[38] 李福乐, 张春, 王志华. 一种流水线结构模数转换器的前端电路及其时序控制方法: 中国, 201310146910.6[P]. 2017-03-15.
[39] 胡世杰, 王自强, 黄柯, 郑旭强, 李福乐, 马轩, 俞坤治, 张春, 王志华. 高速时钟数据恢复电路中的时钟相位判断电路和判断方法: 中国, 201210478209.X[P]. 2015-10-14.
[40] 董晶晶, 张凌炜, 姜汉钧, 池保勇, 李福乐, 张春, 王志华. 一种可重构多频段收发机射频前端: 中国, 201210394086.1[P]. 2014-07-23.
[41] 李福乐, 李玮韬, 杨昌宜, 王志华. 一种参考电压的驱动电路: 中国, 201210362016.8[P]. 2016-07-20.
[42] 李福乐，宁彦卿，姜汉钧，陈新凯，王红梅. 一种无线射频发射机: 中国, 201110140426.3[P]. 2016-04-20.

所出版的专著

[1] 李玮韬，李福乐，王志华. High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications. New York: Springer-Verlag New York Inc., 2017.
[2] （美）W.Alan Davis, （美）Krishna K.Agarwal. 射频电路设计. 李福乐 等 （王志华 审校）, 译. 北京: 机械工业出版社, 2005.