This paper presents a low-offset dynamic comparator using an input offset-cancellation technique. The offset of a dynamic comparator is mainly determined by the dynamic preamplifier. The proposed technique achieves input offset-cancellation under the assistance of the dynamic preamplifier and input-series capacitors, without quiescent current. The offset resulting from both threshold voltage mismatch and sizing factor mismatch can be cancelled. A prototype comparator is implemented by 65-nm CMOS technology with an area of 127μm2. The simulation results show it achieves 1.16-mV offset at 1-sigma(σ), while its counterpart without offset-cancellation achieves 8.91-mV offset at 1-sigma(σ). After post-layout simulation, the offset at 1-sigma(σ) only slightly increases to 1.56-mV. The power dissipation is 135-μW from a 1.2V supply, at 500MHz operating.