This paper presents an 8-bit 1.6GS/s successive-approximation-register analog-to-digital converter (SAR ADC) with alternate comparators. To enhance dynamic performance and speed, a dither-based background relative offset calibration and a fast SAR logic are proposed. In the background calibration, the least significant bit (LSB) can indicate the polarity of the relative offset between comparators after injecting dither into the input, facilitating calibration without extra phase. The fast SAR logic, which includes a trigger logic and a digital-to-analog converter (DAC) control logic, features a 3-logic-gate delay, resulting in a reduced bit duration. These techniques are validated by a prototype 8-bit SAR ADC in 28 nm CMOS technology, exhibiting the highest speed (1.6 GS/s) and smallest area (0.0008 mm2) among single-channel 8-bit SAR ADC. With a Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) improves from 31.6 dB to 43.6 dB, while the spurious-free dynamic range (SFDR) improves from 38.7 dB to 58.3 dB after offset calibration. It consumes 5.73 mW from 1-V supply, yielding a Walden FoM of 29.0 fJ/conv-step.