This paper presents a dual-channel 11-bit 100MS/s hybrid SAR ADC IP. Each channel adopts flash-SAR architecture for high speed, low power and high linearity. Dynamic comparators in the coarse flash ADC and the fine SAR ADC further contribute to the reduction of power consumption. A gate-controlled ring oscillator generates a multi-phase clock for SAR logic, thereby allowing it asynchronously triggers the comparator in the fine SAR ADC in high speed. MOM capacitors with fully shielded structure provide enough matching accuracy without the need for calibration. This design was fabricated in SMIC 55nm low leakage CMOS technology and the active area of dual-channel (I-Q) ADC is 0.35mm2, the core area is 0.046 mm2. It consumes 2.92mA at 1.2V supply, for dual-channel too. The effective number of bits (ENOB) is 9.90 bit at 2.4MHz input frequency, and 9.34 bit at 50MHz. Leading to a FOM of 18.3 fJ/conversion-step