An 11bit 150MS/s dual-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) IP for wireless transceiver is presented in this paper. Each channel adopts sub-range SAR architecture, which combines bootstrap switches for high linearity, gate-controlled ring oscillator (GCRO) for high speed and dynamic comparator for low power. In addition, division in Capacitive Digital-to-analog Converter (CDAC) avoids capacitors connecting to common-mode voltage (VCM) and the switch transistors incompletely switching on. The 11 bit 150MS/s prototype is fabricated in smic55nm low leakage CMOS process. The active area of dual-channel ADC IP is 0.35 , while the core area is 0.046 . A single channel consumes 2.04mA current and achieves an SNDR of 60.9dB at 150MS/s sample rate and 1.2V supply and reference, resulting in a FOM of 17.9fJ/Conversion-step. Measured DNL and INL are +0.99/–0.81 LSB and +2.21/–1.37 LSB