This paper presents a 10-bit 32MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power Wi-Fi receivers. To boost the conversion speed with high power-efficiency, an asynchronous SAR ADC architecture with a split-capacitor array, full custom dynamic logic and a dynamic comparator are adopted. Furthermore, based on a gate-controlled ring oscillator (GCRO), the multi-phase clock generator in the proposed SAR ADC triggers the asynchronous SA conversion directly without bit-by-bit feedback operation from SA logic to the clock generator. Implemented in a 180nm CMOS technology, post-layout transient simulation with noise shows that the ADC achieves a SNDR of 59.3dB and a SFDR of 72.3dB with an input frequency of 15.14MHz. The ADC core consumes 1.38mW at a 1.8-V supply, resulting in a figure-of-merit (FoM) of 61fJ/conv.-step.