A 10 bit, 120 MS/s two-channel pipelined analog-to digital converter (ADC) is presented in this paper. The ADC is featured with improved switch by using body effect to improve its conduction performance. A new scaling down strategy is proposed to get more efficiency in the layout design. Implemented in a 0.18-μm CMOS technology, the ADC’s prototype occupied an area of 2.05x1.83 mm2. With a sampling rate of 120-MS/s and an input of 4.9MHz, the ADC achieves a spurious-free-dynamic range (SFDR) of 74.32 dB and signal-to-noise-and-distortion ratio (SNDR) of 55.34 dB, while consuming 220-mW/channel at 3-V supply.