The phase-domain analog-to-digital converter (Ph-ADC) is proved to be more power efficient than traditional amplitude ADCs in wireless receivers . A low power multi-step Ph-ADC for zero intermediate frequency (IF) GFSK receivers as defined in Bluetooth low energy protocol is proposed in this paper. With dedicatedly designed binary code scheme and multi-step operation, the Ph-ADC requires only 52 current elements and one comparator, in contrast to the design in literature using 260 current elements and 8 comparators. Non-idealities due to transconductance errors and offset errors are theoretically analyzed, followed by a design strategy to minimize trip point errors. Simulation results show that the digital intensive Ph-ADC consumes only 7.9 μA current from a 1.8 V supply when implemented in a 180 nm CMOS process. Monte-Carlo simulations show that the maximum trip point error is only 2.3°, which is less than 1/8 least significant bit. When the Ph-ADC is used in a GFSK demodulator, the required IF Eb/N0 is 13.5 dB to achieve a bit error rates of 0.1%.