An 8-bit 1MHz Successive Approximation Register (SAR) A/D has been developed. It employs two sampling bootstrapped switches, a charge redistribution DAC, a dynamic comparator and a digital control block. The presented ADC is fabricated in a 0.5?m CMOS process and the active core area is 0.5*1.0 mm2. Measurement results show the A/D achieves 49.8dB peak SNDR and 68.7dB SFDR. The effect number of bits (ENOB) is 7.98. When the frequency of input signal is up to 5.477MHz, the A/D can also achieve more than 7 ENOB. The total power dissipates is 2.5-mW.