This paper proposes a digital background calibration algorithm for pipelined analog-to-digital converters (ADCs). The algorithm doesn’t modify pipeline stages and only needs simple calibration logic. Based on the analysis of the output codes, the algorithm estimates the bit weight of each stage and calculates the outputs. To verify the algorithm, a 13-bit pipelined ADC with 1.5-bit/stage architecture is simulated with nonideal factors such as random capacitor mismatch, comparator offset, finite opamp gain, opamp noise and opamp offset taken into account. SNDR is improved from 43.9dB to 76.5dB. Monte Carlo simulation result demonstrates the algorithm is robust to random circuit parameters.