This paper presents a new digital background calibration technique for pipelined ADC, and the design scheme of a 13-bit 50MS/s pipelined ADC with the proposed calibration technique. The real weight of each digital bit can be recalculated by making statistics of occurrence frequency of the output codes from comparator and backend ADC. Multiple errors from different error sources, such as finite Opamp gain and capacitor mismatch can be calibrated with the recalculated real weight. The circuit design was implemented in UMC 0.18μm mixed mode CMOS technology with 1.8V supply voltage. The input-output relationship of each transistor level stage circuit was got by SPECTRE simulation, and was calibrated in the top-level behavior model. Simulation results show with 50MHz sampling rate and 5MHz input signal, the proposed calibration technique increases SFDR from 44.1dB to 102.2dB, SNDR from 40.9dB to 79.9dB and ENOB from 6.5bit to 12.98bit.