A 14-bit 250MS/s low power pipeline analog-to-digital converter (ADC) implemented in a 0.18渭喂畏 CMOS process is presented in this paper. A SHA-less 3.5-bit front-end is adopted to achieve low power design. An aperture error eliminating technique and flash ADC optimization design techniques such as capacitor splitting, interpolation, and offset calibration, are both used to achieve wideband input even for the front-end with resolution up to 3.5-bit. The post simulation results show this ADC achieves an SNR of 74.6 dB, an SNDR of 74.4 dB and an SFDR of 87.1 dB with a 70MHz input signal, while maintaining an SNR > 72.5 dB and an SFDR > 77.4 dB up to 900MHz input signals. The ADC consumes 120mW from a 1.8 V supply.