A 320MS/s 14bit pipelined SAR ADC in 40nm CMOS technology is presented in this paper. Considering the non-ideal factor of key node caused by much modules connected to here, and mismatch between inter-stage residue amplifier and comparator in SAR ADC, both of them have bad effect on the performance of the pipelined SAR ADC. To solve these problems, this design uses dynamic amplifier alternately function as the pre-amplifier in the comparator for background gain calibration, the pre-amplifier in the comparator for SAR ADC conversion and the inter-stage residue amplifier. The multiplexing of dynamic amplifier relieve the interference of key node and the parasitic capacitance of capacitor array top plate. And a background gain calibration scheme is proposed for the dynamic amplifier.