In this paper a specific implementation of the transceiver controller is presented, based on a high speed serial interface (HSSI) protocol-JESD204B. The implementation of this protocol provides less pin counts, lower complexity and more accurate timing control than the traditional parallel data transportation from ADC to DAC. This paper gives a design of the transceiver controller and the verification system. The design ensures the data synchronization of different lanes. The experiments show that the transceiver controller can work correctly and the verification system can transmit and receive data correctly under the data rate of 4Gbps per lane on the Stratix V 5SGXEA7K2F40C2 developing board. The frequency of the verification system can reach 400MHz and the resources used will be listed in the paper.