This paper presents a novel architecture to achieve a 10bit pipeline ADC based on SAR technique which is used in a CMOS image sensor. A theoretical analysis is proposed to determine the high resolution MDAC and the suitable value of unit capacitor. The high-resolution first stage, the half-gain MDAC and the dynamic comparator are adopted to improve the linearity and to reduce the power. To satisfy the strict area requirement of CMOS image sensor, the layout is carefully designed. This pipelined SAR ADC is designed and fabricated in SMIC 180nm CMOS technology. Simulation results show the ADC achieves 60.37dB signal to noise distortion ratio (SNDR) and 76.37dB spurious free dynamic range（ SFDR） . The effective number of bits (ENOB) achieves 9.74 bit. The core area is 140umⅹ280um, about 0.04 mm2. The power dissipation is 9.8mW in typical case under 2.8V supply.