The DDR2 controller module was extracted from LEON3 open-source processor. Relevant read and write tests were accomplished. Moreover, the DDR2 controller IP was connected to NiosII CPU based on Altera’s Qsys platform .The SoPC system completed hardware and software co-verification. Results showed that 287 ALUTs of StratixIV FPGA core chip were occupied and the DDR2 SDRAM operating frequency was up to 200MHz. Meanwhile, a set of method was developed to connect IP with AHB bus interface to NiosII’s Avalon bus and complete the FPGA verification.