A low-power 24-bit Δ-Σ ADC designed for ECG(electrocardiogram) acquisition with dynamic adjustment is presented. Using a 3rd order 5-bit modulator structure, the ADC can achieve 120.4 dB SNR(Signal-Noise Ratio) and 19.71 bit ENOB in high-speed mode; 108.4 dB SNR and 17.71 bit ENOB in low-speed mode. By adding a QRS detector with dynamic adjustment, the ADC can adjust the working mode according to the wave form of ECG. As to a typical ECG, the amount of data with dynamic adjustment can significantly reduced to 62.5% as compared to the conventional design, while the average power consumption of ADC can be reduced to 101.5 μW, 66.7% of the ADC with no dynamic adjustment.