This paper presents a 6-8GHz 2Mb/s Chirp-UWB (C-UWB) transceiver implemented in 65nm CMOS. The transceiver performs burst-mode transmission with an optimum duty-cycle control by utilizing a steep digital gradient generation circuit in the transmitter. To enhance sensitivity and interference immunity, a slope detection based decision method is employed in the receiver by utilizing a 2-bit continuous-time sample-and-hold ADC, which obtains more information of the received signal compared to the single-threshold decision. The 2Mb/s transceiver consumes 1.8mW from a 1V supply, achieving an energy efficiency of 0.9nJ/bit.