A half-rate digital clock and data recovery (CDR) circuit for 60GHz 10Gbps QPSK receiver in 65nm CMOS is presented. Analog blocks are replaced by digital equivalents to save power and area, reduce PVT variation and improves testability. Voltage-controlled oscillator (VCO) is replaced by phase interpolator (PI) which is controlled by digital control signals. Half-rate Bang-Bang phase detector (BBPD) is used to decrease the clock rate, thus, double edge-triggered sampler is needed in such multi-Gbps CDR. The CDR consumes 17.44mW with a supply voltage of 1.0V, and operates from 1.25Gbps to 6.4Gbps with a maximum clock frequency offset tolerance of 40 ppm.