This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with the tap differential pairs within clock-control summers array (CCSA) to accomplish the 2nd and 3rd tap stages design. The total power consumption of the 3-tap DFE is 27mW under 1V, achieving 0.67 pJ/bit energy efficiency.