This paper proposed an ASIC implementation of JPEG2000 encoder, which functionally consists of two parts： Discrete wavelet transform （DWT） and Embedded block coding with optimized truncation （EBCOT）. For DWT, a Spatial combinative lifting algorithm （SCLA） based scheme with both （5,3） reversible and （9,7） irreversible filters is adopted to reduce 50% and 42% multiplication computations respectively compared with the conventional Lifting based implementation （LBI）. For EBCOT, a Dynamic memory control （DMC） strategy of Tier-1 encoding is adopted to reduce 60% scale of the onchip wavelet coefficient storage and a subband parallelprocessing method is employed to speed-up the EBCOT Context formation （CF） process; an architecture of Tier-2 encoding is presented to reduce the scale of on-chip bitstream buffering from full-tile size down to three-codeblock size and accurately control the compression bit-rate （with 95% precision）. This encoder is capable of JPEG2000 compression with a 1280 × 1024 pixel （YUV422 full color） at 20frames/s employing 100MHz working clock. Power consumption is 465mW at 1.8V and 100MHz.