A source-synchronous serial link receiver with an adaptive quarter-rate 2-tap DFE and a baud-rate CDR is demonstrated. The data-sampler-lane (DSL) of the DFE uses the combination of the soft-decision technique and a new dynamic structure to achieve a power efficiency of 0.24mW/Gb/s. The error-sampler-lane (ESL) based on the same dynamic structure is shared by the DFE adaption logic and baud-rate CDR logic to save power and area. A hybrid alternate clock scheme is implemented to satisfy the timing requirement and reduce power consumption further. This receiver fabricated in 65nm CMOS operates from 15 to 28Gb/s, and compensates for a Nyquist channel loss of 32dB with 0.42UI timing margin at 25Gb/s for BER=10-12. The active area is 0.18mm2 and the power consumption is 48mW at 25Gb/s from a 1.2V supply.