A 0.1-1.5GHz Software-Defined Radio (SDR) transmitter has been implemented in 65nm CMOS. To solve the harmonic-mixing issue, a proposed two-stage harmonic rejection (HR) power mixer is integrated in the transmitter, which can directly drive the power amplifier. The first-stage and second-stage HR work in current mode, via current mirror and current division circuits respectively, different from other harmonic rejection methods. With the maximum gain RF I-to-V conversion, the simulated conversion gain of the power mixer ranges from 13.2 to 16dB. The proposed power mixer achieves >65dB HRR3 and >68dB HRR5, respectively, over the covered frequency band without any calibration in various process corners. The simulated OP1dB is between 9.4dB and 12.3dB, large enough to drive the following PA.