This paper presents a high-speed wide-band continuous-time (CT) Delta-Sigma (ΔΣ) modulator. The modulator is modeled in MATLAB SIMULINK with a single-loop 3rd-order 4-bit quantization structure. By modeling non-ideal factors such as limited OPAMP DC gain, limited gain bandwidth product (GBW) and excess loop delay (ELD), design properties of circuit module are determined. The modulator is designed and implemented in UMC 180nm process. High-speed dynamic latch comparator with low-noise and high-resolution is designed for quantization. Dynamic element matching (DEM) module with low latency is included to suppress DAC mismatching. A direct feedforward path is introduced by RPI to compensate for excess loop delay (ELD). The modulator achieves a pre-layout 83dB signal to noise distortion ratio (SNDR) with a figure of merit (FOM) of 220fJ/conv-step and occupies 0.1mm2 active area.