A chirp-UWB transceiver which transmits a 1.3 bit information in a single pulse clock period by embedding pulse position information in the chirp FSK modulation is implemented in 0.18μm CMOS. A digital-intensive chirp-UWB transmitter by employing digital ramp generator and a digitally-controlled oscillator (DCO) is designed. In the receiver, a dual-BPF based regenerative architecture is employed to relax the Q requirement. The proposed transceiver achieves the energy efficiency of 2.5nJ/b for the transmitter and 24.2nJ/b for the receiver at the data rate of 1.6Mb/s.