SRAM compiler needs to configure SRAM of various word widths and sizes. To meet this need, SRAM array and periphery circuits should be designed as configurable and reusable. In this paper, array partition, two-stage decoder and sense amplifier with local timing control based on 0.525um2 6T SRAM cell were applied to achieve high-speed SRAM design for compiler. 512K bits SRAM was verified based on SMIC 65nm CMOS process. 1.12 ns high-speed access time has been achieved as the test result shown.