This paper describes a 10Gb/s analog equalizer applied to transmitter. The equalizer consists of a continuous time linear equalizer (CTLE), with a shunt and double-series peaking network, which is used to enhance the bandwidth of the circuit and to boost the high frequency content of the signal. This paper deduces the circuit's transfer function and proposes a design guidance to circuit design. The circuit is fabricated in 0.18um CMOS technology. The measurement results show that, when the chip delivers 10Gb/s PRBS7 data over a 6.3 inches FR4 channel, the output peak-to-peak jitter is 34ps. This circuit also works as a driver and has a good impendence matching. The power consumption of the equalizer is 30.2mW for 1.8V supply.