The paper presents a hardware implementation of a low-power and low-area JPEG (Joint Photographic Experts Group) compressor. The compressor uses a 4x4 divided-block to reduce the hardware complexity. The 4x4 compressor employs an optimized 1D-DCT algorithm, which contains only one multiplication. A new controlling architecture with 16 registers is used in transition buffer of 2D-DCT which reduces 37.5% latency and 51% area compared with traditional transposition architecture (two RAMs architecture). Apply similar new controlling architecture with 16 registers in zigzag buffer, 67.5% latency and 51% area can be reduced. The test result of several color images shows that high compression ratio (over 80%) can be achieved with high quality image reconstruction (PSNR over 30 dB). This JPEG compressor is carried out in 0.18 um CMOS technology. The area and power consumption of the designed compressor are 0.46 mm2 and 0.9mW, respectively.