This paper describes a DS dithered time-to-digital converter (TDC) design for all-digital phase-locked loops (ADPLLs). Different from other DS modulated TDCs, the proposed TDC employs a DS delay-locked loop (DLL) to achieve both noise-shaped dithering and PVT-insensitive time resolution. Simulation results show that the proposed TDC significantly improves the fractional spur performance even with TDC nonlinearity considered. The TDC designed in 65nm CMOS occupies an area of <0.06mm2 and consumes 2.2mW.