Built-In Self-Repair (BISR) with Redundancy is an effective yield-enhancement strategy for embedded memories. This paper proposes an efficient BISR strategy which consists of a Built-In Self-Test (BIST) module, a Built-In Address-Analysis (BIAA) module and a Multiplexer (MUX) module. The BISR is designed flexible that it can provide four operation modes to SRAM users. Each fault address can be saved only once is the feature of the proposed BISR strategy. In BIAA module, fault addresses and redundant ones form a one-to-one mapping to achieve a high repair speed. Besides, instead of adding spare words, rows, columns or blocks in the SRAMs, users can select normal words as redundancy. The selectable redundancy brings no penalty of area and complexity and is suitable for compiler design. A practical 4K × 32 SRAM IP with BISR circuitry is designed and implemented based on a 55nm CMOS process. Experimental results show that the BISR occupies 20% area and can work at up to 150MHz.