A PVT-insensitive all-digital clock generation system architecture has been presented. As a key block in ADPLL, the TDC is based on DLL and can exactly cover one period of ADPLL output. Compared to conventional open-loop TDC, the proposed one significantly reduces INL of delay line to decrease fractional spur of ADPLL. Besides that, thermometer output of proposed one makes phase information simpler to process while conventional one needs more calculation. Designed in 65nm, detailed schematic of TDC is shown. Layout of ADPLL takes an area of 0.71mm2. TDC occupies 0.05mm2 while has a power consumption of 2.1 mW.