A wide-tuning low-cost PLL architecture withnegligible loop filter area is presented. To overcome the staticphase error or reference spur problem of the conventional type-IPLL over broad frequency tuning range, a  DAC based realtimefrequency acquisition aid method is employed in the PLLvoltage domain. Different from other  based frequencyacquisition methods mainly used for the type-II all-digital PLL(ADPLL), the proposed method provides inherent quantizationnoise reduction by the PLL loop filter. Simulation results verifythat significant reference spur reduction as well as  noisereduction can be achieved with the proposed architecture.