Sub-threshold digital circuits is an ultra-low power technology for applications that do not require high speed. This paper provides circuit design methods for sub-threshold standard cells including size, drive capability, and structure for a sub-threshold digital standard library. Simulations of a 32-bit data-path designed using the sub-threshold cells show that the noise margin of the new data-path is improved by 8%, the frequency by 42%,the energy consumption by 27%,the Energy-Delay Product(EDP) by 49% and the leakage current by 64% compared with the convention library.