The dual-path ΔΣ fractional-N PLL provides linearcharge pump gain and small VCO gain variation good for digitalmodulation but could suffer from long settling time due to thenarrowband coarse-tuning control path. By employing a dynamicgain-bandwidth control scheme for both paths, a high-gaincoarse-tuning loop can be utilized for fast settling time. Whilemaintaining a small control voltage range in the loop filter duringfrequency acquisition, the proposed method makes bothcoarse-tuning and fine-tuning paths active with compensatedopen-loop gain design, which results in a smooth transition fromthe transient mode to the normal mode. A prototype 4GHzdual-path fractional-N synthesizer is implemented in 90nm CMOS,showing that less than 68μs transient settling time with 91MHzfrequency step can be achieved with the nominal bandwidth of60kHz.