This paper describes a low-noise ΔΣ fractional-NPLL utilizing a mixed-mode triple-input LC VCO. An analogdual-path VCO control relaxes the nonlinearity problem of theΔΣ fractional-N PLL, while a combination of discrete andcontinuous tuning methods for the coarse-tuning controlsignificantly alleviates noise and coupling problems caused by ahigh coarse-tuning control path. A 3.6GHz ΔΣ fractional-N PLLimplemented in 65nm CMOS exhibits nearly –100dBc/Hz inbandnoise contribution and –75dBc fractional spurperformance at 500kHz offset frequency from a 1.8GHz carrier.