A low power voltage reference is implemented in a standard 0.18 μm CMOS process. The temperature coefficient (TC) of 7 ppm/°C is achieved in virtue of the output stage which consists of two transistors operating in subthreshold region and saturation region respectively. This kind of output stage is used to adjust the output voltage and compensate the curvature. The line sensitivity is 200 ppm/V in a supply voltage range of 1-3 V, and the power supply rejection ratio (PSSR) is -85 dB and -42 dB at 100 Hz and 10 kHz, respectively. The maximum supply current is 240 nA. The chip area is 0.016 mm2.