This paper describes the architecture and circuit design of a low data rate FM-UWB transmitter. A Δ-Σ fractional-N PLL with a multi-phase relaxation oscillator is designed to enable sub-carrier modulation with reduced quantization noise. The triangular waveform output of the relaxation oscillator directly modulates an LC VCO to have the UWB-compliant spectrum. The center frequency of the LC VCO is quasi-continuously tuned by a Δ-Σ DAC based frequency-locked loop with the power consumption of 1.1mW. The 3.43-4.03GHz FM-UWB transmitter implemented in 0.18μm CMOS consumes the total power of 9.6mW.