This paper describes a?circuit?design?methodology to?optimize?both?power?and?jitter?performances of the inductorless voltage-controlled oscillators (VCOs) by utilizing?an?on-chip?supplynoise?monitoring?circuit. As the phase-locked loop (PLL) has a sensitive response to the?noise?frequency near the loop bandwidth, detecting low frequency tones up to the PLL bandwidth is considered for a?supply?noise?monitoring?circuit, which makes it possible to?design?a low cost semi-digital?noise?monitoring?system. This work affirms the importance of?optimizing?the voltage swing amplitude of the inductorless?VCO, which sets a fundamental trade-off between low?power?and low?noise?performances. Transistor level simulations are done to verify the effectiveness of the proposed method for the ring?VCO?and the relaxation?VCO. ? 2010 IEEE.