An ESD protection system for deep submicron chips is designed using a systematic view. After every power domain is protected separately, crosscoupled ESD diodes are used to connect the isolated power domain grounds. The problems existed in traditional output ESD protections are analyzed, moreover, an output ESD protection is designed in a safe manner. The prototype test chip was fabricated in a 0.18μm CMOS technology, the test result verified the efficiency of the ESD design.