Considering that RFID application is becoming increasingly wider, it is urgent to impove the performance of RFID tag. For passive RFID tag, one of the important specifications is operating distance, which can be extended by reducing the power consumption of tag. This paper presents the digital baseband design of UHF RFID tag based on ISO18000-6(C) protocol and introduces details of some low power design technologies. In the beginning of this paper, RFID application and ISO18000-6(C) protocol are introduced, then the architecture of the design is described. A series of low power design strategies, such as dynamic control of clock, reuse of registers, using counter and combinational logic instead of shift registers, asynchronous counter, clock-gating, etc, are shown in the fourth part. The simulation results indicate that the power of digital baseband processor has been reduced effectively, which is about 4.8μw under 2.5MHz clock frequency with 1.0V power supply. And the chip which implemented the first three strategies consumes 8.03μW under 2.5MHz clock frequency with 1V power supply.