The design of a 12 bit 80 MS/s CMOS pipelined ADC was presented for the application of baseband signal processing. A 2.5 bit stage circuit was used in the first stage. Bootstrap switches were used in S/H to improve the linearity of ADC. Stage circuit scaling was used to save area. Folded cascode gain bost amplifier was optimized for fast settling and power saving. This design was implemented in HJTC 0.18 μm standard CMOS process with 1.8 V supply voltage. A 8 MHz, 1 V_(p-p) sine signal was sampled by 80 MHz clock. Post-simulation results show that an ENOB of 11.10 bit and an SFDR of 80.16 dB are achieved. The chip consumes a power of 155 mW.