A low-power, medium-speed and medium-resolution enhanced successive approximation ADC is described, which is used as an interface of DSP. Its DAC adopts a split capacitive array in order to lower chip size, which uses dynamic element matching technique in the most three significance bits so as to improve the ADC performance. Four pre-amplifiers and a latch consist of the comparator, and offset cancellation technique is employed. The digital logic part is full-custom designed, which coordinates the analog circuits to accomplish successive approximation and can power down the whole ADC. The chip is fabricated in UMC 0.18m Mixed Mode CMOS technology, the layout occupies an area of 2.2mm×1.5mm. The post-simulation results show that, the ADC achieves 12bit at 1MSps sampling rate and consumes only 2.6mW power using a 1.8V Supply voltage.