Folding and interpolating architecture are widely used in designing high-speed ADCs. A new time-interleaving technique combined with folding and interpolating techniques was presented,with which the conversion rate almost doubled while power and chip area remained.Based on bit synchronization technique,a new encoding mode was designed which could simplify coarse channel design.An 8 bit 400 MS/s CMOS folding and interpolating ADC was designed based on the techniques above.The ADC draws about 110 mA from a 1.8 V supply and the chip size is only 1 mm×0.8 mm. The ADC achieves 47.2 dB SNDR and 57.1 dB SFDR at Nyquist input.