ΣΔ-A/D is insensitive to fabrication and compatible with today’s VLSI technology. It can also reach high resolution and flexibility. This paper shows the whole design of a single-loop 3rd-order ΣΔ modulator for 80dB SNDR 100kHz signal bandwidth applications with 3.3V power supply. The modulator uses class AB OTA to meet the requirement of high slew rate with relatively low static power dissipation. The chip is fabricated in UMC 0.18um CMOS technology. With an oversampling ratio of 60 and a clock rate of 12 MHz, the modulator achieves a 75.7 dB SNDR and 98dB SFDR in chip measurement. The whole chip size including PADs is 1.7mm*1.3mm.