Two VLSI architectures were developed for JPEG2000 encoder IP design, the discrete wavelet transform (DWT) and the embedded block coding with optimized truncation (EBCOT) for JPEG2000. The DWT design is based on the spatial combinative lifting algorithm (SCLA) with a 9/7 filter, which requires 7/12 of the computations in the conventional lifting algorithm. The EBCOT design uses parallel processing and dynamic memory control (DMC) architecture, which greatly speeds up the coding process and achieves higher hardware utilization. These two architectures can also be used as independent, efficient IP cores for various real-time imaging applications, such as remote surveillances and digital still cameras.