A 3.6 GHz fractional-N PLL utilizing high-order digital modulation and weighted 13-tap finite impulse response (FIR) filtering for low spur and enhanced noise reduction is implemented in 65 nm CMOS. The prototype PLL exhibits nearly -100 dBc/Hz in-band noise contribution and -126.8 dBc/Hz phase noise at a 3 MHz offset from a 1.8 GHz carrier. With 5th-order single-loop ΔΣ modulation, the fractional spur levels of -65.6 dBc and -58.5 dBc are achieved within the bandwidth and near the bandwidth, respectively.