A CMOS PLL clock synthesizer for ADC clock applications was designed．Based on Type I PLL architecture，a new linear model for system-level analysis was presented，and an improved on-chip passive discrete-time loop filter was proposed，which drastically shorten time-to-market. The 21.88 MHz clock synthesizer demonstrator test chip has been fabricated in a mixed-signal 0.18um CMOS process．The charge pump and VCD core on the chip consume 410uA of power from a 1.8-V supply．The synthesizer has a phase noise of -114 dBc/Hz at 1MHz offset.