A new method is presented for reducing the settling time of a feedback amplifier in a charge-transferred pipelined A/D converter to improve the A/D conversion speed. An extra clock phase is introduced in the sampling phase of the pipelined stage to release the charge on the capacitors which are going to be connected to the upper stage amplifier output. The initial step of the settling response is then optimized which reduces the maximum settling time. The proposed method is proved useful for commonly-used pipelined architectures, especially for those with low stage resolution, small op-amp linear input ranges, low settling precision requirements, and small capacitor scaling factors. The conversion period can be reduced by more than 30% with this method in a 1-bit-per-stage or 1.5-bit-per-stage architecture with a small op-amp linear input range and no capacitor scaling.