A novel capacitor mismatch calibration technigue for pipelined analog-to-digital conversion is presented. The nonlinear capacitor mismatch error is reduced to the second order through an algorithmic circuit method，which involves charge summing，capacitors exchange，and charge redistribution. Simulation results confirm the observation and a case of 12-bit INL realized by 4-bit capacitor matching is shown. Compared to the conventional circuit，the new approach is still a simple implementation by reguiring only some extra analog switches.On the other hand，the conversion speed is slowed because one conversion now reguires three clock phases instead of two. Therefore this technigue is most suitable when moderately high speed combined with high resolution is reguired.