A VLSI architecture was developed for lossless or near-lossless video compression in a JPEG-LS encoder by removing features that limit parallel computations and increase power consumption. The architecture includes a mode decision module, clock controller, 3 linear parallel pipelines, and a two-tier data packer. Computations are fully pipelined in these modules for real time data processing. The clock management mechanism with 4 clock regions and a dedicated clock controller prevents bottlenecks in the calculations and shuts off the clocks in idle modules to reduce overall power consumption by 15.7%. The low power consumption, high data processing rate JPEG-LS encoder is being used in a wireless endoscopy system.